Digital Logic Design (EENG 2710) Spring 2008

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Instructor: Parthasarathy (Partha) Guturu           Homework -1    Homework - 2     Homework - 3   Project  
Faculty Office: NTRP B-235
Phone: 940-891-6877
Email: guturu@unt.edu
Teaching Assistant: Pratima Krishna
Class Hours: M/W 9:30 AM - 10:50 AM
Class Room: NTRP B-242, Computer Lab.
Office Hours: M 11:0 0 PM-1:00 PM. Students unable to see me during these times may request an appointment.
Prerequisite: Math 1720

Reference Book:
1. Digital Logic Circuit Analysis & Design, 1st Ed. V. P. Nelson, H. T. Nagle, J. D. Irwin, and B. D. Carroll, Prentice Hall, 1995. ISBN: 0-13-463894-8.
Other References:
1. Xylinx manuals for Logic Design using Schemas (Contact Pratima for accessing the relevant information)

2. Contemporary Logic Design, 1st ed. Randy H. Katz, Benjamin/Cummings Publishing Company, 1994. ISBN: 0-8053-2703-7.

3.Digital Design. M. Morris Mano, 3rd Edition, Prentice Hall, 2001. ISBN: 0130621218.

4. A power-point presentation is used to provide some information to support and supplement a student-centric problem/project-oriented learning methodology.

5. Good documentation is an essential component of a successful project. Please see the following report (in PDF) on how to write project reports.

Attendance Policy:     In view of the continuous evaluation strategy adopted by the instructor, perfect attendance is recommended for those aspiring to get good grades.

Grading Policy:          Regular quizzes/class assignments and tests: 50, Project: 30 and Final Exam: 20.

Academic Dishonesty: Honesty is the best policy. Cheating will not be tolerated. Anyone found guilty of cheating on a test or assignment will be awarded an F grade for the course. Discussions of problems and assignment with your classmates is welcome and encouraged, however, sharing of solutions is not. If you need help, you should ask the instructor. Cheating includes, but is not limited to, all forms of plagiarism and misrepresentation. For your rights and responsibilities please refer to http://www.unt.edu/csrr

Statement regarding Disabled Students: The Faculty of Electrical Engineering including this instructor cooperates with the Office of Disability Accommodation (ODA) to make reasonable accommodations for students with certified disabilities (cf. Americans with Disabilities Act and Section 504, Rehabilitation Act). If you have not registered with ODA, we encourage you to do so immediately and present a written accommodation request along with an appropriate documentation from the Dean of Students Office http://www.unt.edu/oda/, on or before the 2nd week of class.

Final Exam Date and Time: TBD.

Course Outline:

1.      Digital and analog systems- an introduction and historical perspective                     (1 week)

2.      Number systems and codes                                                                                         (1 week)

3.      Boolean Algebra, Switching functions and canonical forms                                      (2 weeks)

4.      Circuit minimization, Analysis of combinational circuits, and  Timing issues        (1.5 weeks)

5.      Top-down Modular Design of Combinational Logic                                               (1.5 weeks)

6.      Sequential Circuit Elements- Latches and flip-flops                                                  (1 week)

7.      Modular Sequential Logic- Counters and shift registers                                             (2 weeks)

8.      Analysis of synchronous sequential circuits                                                               (1 week)

9.      Design of synchronous sequential circuits                                                                  (2 weeks)

10.  Analysis and Design of asynchronous sequential circuits                                          (1 week)

11.  Digital Logic Testing                                                                                                   (1 week)

Course Objectives:

The main objectives of the course are to facilitate the students to achieve the highest levels in the Bloom's 6-level Learning Taxonomy so that they, at the end of the course, will be able to-

  1. Know what the digital systems are, how they differ from analog systems and why it is advantageous to use the digital systems in many applications.
  2. Comprehend different number systems including the binary system and Boolean algebraic principles
  3. Apply Boolean algebra to switching logic design and simplification.
  4. Analyze a given digital system and decompose it into logical blocks involving both combinational and sequential circuit elements.
  5. Synthesize a given system starting with problem requirements, identifying and designing the building blocks, and then integrating blocks designed earlier
  6. Validate the system functionality and evaluate the relative merits of different designs.

Relationship between the Program Outcomes and Course Objectives:

Successful achievement of the course objectives will contribute to the following outcomes of the BSEE program related to equipping the students with:

  1. An ability to apply knowledge of Boolean Algebra to Digital Circuit minimization [ABET (a)]
  2. An ability to design digital systems from component (gate) level to meet desired needs [ABET(c)]
  3. An ability to identify, formulate, and solve engineering problems related to digital system design using project-based learning approach [ABET (e)]
  4. An ability to communicate effectively[ABET (g)]
  5. An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice  (here you learn Xylinx Software tool) [ABET (k)]